Schottky diodes are much used in modern electronic devices, especially integrated circuits (ICs). However, their performance and area efficiency are often less than ideal. Area efficiency refers to the chip area needed to obtain a Schottky diode of a given forward conduction capability, more precisely, the area efficiency is the ratio of the Schottky contact area to the total device area. For a given Schottky contact work function and Schottky contact area, the larger the overall device area for a given current handling capability, the lower the area efficiency. Excess reverse bias leakage is also often a troublesome performance limitation. Means and methods used in the prior art to limit the reverse bias leakage have typically caused a significant increase in the total area occupied by the Schottky device and therefore a further decrease in the area efficiency. It is well known that manufacturing cost of semiconductor devices and integrated circuits (ICs) is directly related to device and chip area. The larger the chip area needed to contain the required devices, the higher the manufacturing cost since the chips are generally batch fabricated in wafers of fixed diameter. A bigger chip means fewer chips per wafer and thus higher individual chip cost. Another consideration for Schottky diodes included in integrated circuits (ICs) is that they are desirably formed using the same technology and processing steps available for forming the IC. This complicates the problem of manufacturing area efficient low leakage Schottky diodes since the available manufacturing process steps are constrained by the process needs of the remainder of the IC, and therefore may be less than ideal for forming the Schottky diodes. Thus, a need continues to exist for improved Schottky diode structures using processes that are compatible with available IC manufacturing technology, especially for Schottky diodes having low reverse leakage and good area efficiency.